A typical example of the decoder buffer circuit is illustrated in FIG. 1 of the drawings. The prior-art decoder buffer circuit 1 is provided in association with an address decoder circuit 2 and selectively activates one of the word lines W0 and W1. The address decoder circuit 2 has a plurality of n+1 input NAND gates 3 to 4, and address bits A0 to An of an n+1 bit address signal and the complementary bits AO to An thereof are supplied to the NAND gates 3 to 4. With the address bits and the complementary address bits, one of the NAND gates 3 to 4 shifts the output node thereof from the inactive high voltage level to the active low voltage level. The decoder buffer circuit 1 is formed by a plurality of two input NOR gates 5 to 6 respectively paired with the NAND gates 3 to 4, and one of the two input nodes of each NOR gate is coupled to the output node of the corresponding NAND gate 3 or 4. The other input nodes of the NOR gates 5 to 6 are commonly coupled to a strobe signal line 7, so that the NOR gates 5 to 6 are activated in the presence of the strobe signal ST of the active low voltage level. The decoder buffer circuit 1 thus arranged allows one of the word lines to go up to the active high voltage level when the active low voltage level is supplied from one of the NAND gate 3 or 4 to the NOR gate 7 or 8 paired therewith. However, when the strobe signal ST is recovered to the inactive high voltage level, all of the NOR gates 5 to 7 remains in the inactive low voltage level.
Each of the NOR gates 5 and 6 are formed by a series combination of two p-channel type field effect transistors 8 and 9 coupled between a positive voltage line and an output node 11 and two n-channel type field effect transistors 12 and 13 coupled in parallel between the output node 11 and a ground node 14. The output node of each NAND gate 3 or 4 is coupled to the gate electrodes of the two field effect transistors 8 and 12, and the strobe signal line 7 is coupled to the gate electrodes of the field effect transistors 9 and 13. The word line W0 or W1 is coupled to the output node 11, so that no conduction path takes place between the positive voltage line 10 and the output node 11 in the absence of the strobe signal of the active low voltage level due to the p-channel type field effect transistor 9 in the off state. However, when the strobe signal goes up to the low voltage level, the voltage level at the output node 11 depends on the complementary functions of the field effect transistors 8 and 12 and, accordingly, the output node 11 is complementarily shifted between the high voltage level and the low voltage level with respect to the output node of the NAND gate 3 or 4.
However, a problem is encountered in the prior-art decoder buffer circuit in that a large number of component transistors are consumed to form the decoder buffer circuit 1 associated with the decoder circuit 2. Each two input NOR gate is formed by four field effect transistors as illustrated in FIG. 2 , and each n+1 input NAND gate needs 2(n+1) field effect transistors. In order to control every word line, it is necessary to provide a series combination of the n+1 input NAND gate and the two input NOR gate, and, for this reason, the total number TR of the field effect transistors associated with every word line is calculated as: EQU TR=2(n+1)+4=2n+6
This results in that a large area on a semiconductor chip is consumed by the peripheral circuits for activation of the word lines. Moreover, a large amount of current is consumed for controlling the word lines.